Study of Epitaxial Silicon Layers with Reference to the Technology of Semi-Conductor Devices

Abstract

Epitaxial silicon layers have been studied, with reference to the technology of semiconductor devices, in order to determine the possibility of developing a new method, which overcomes the limitations associated with the conventional methods for forming PN junctions by introducing impurities into the crystal during growth from the melt or by diffusion. The mechanisms governing epitaxial growth, by silicon vapour and vacuum deposition are reviewed and the most promising adopted for further study and development. This involved the design and construction of apparatus for the growth of layers by the hydrogen reduction of silicon tetrachloride and for control of crystal perfection, layer thickness, layer type and resistivity, as determined by the doping element and its concentration respectively. Methods of evaluating the conductivity, thickness, resistivity, structure, impurity and doping concentration were assessed and the most suitable methods developed. The dependence of the growth of epitaxial layers of controlled properties on nucleation, gaseous impurities in the system and on the type and concentration of the doping elements in the gas system and the substrate, have been established. Lattice defects originating mainly at the substrate-layer interface giving rise to inferior electrical characteristics, can be eliminated by gaseous polishing of the substrate surface and control of the purity of the reaction system. Difficulties have been encountered in controlling the layer thickness in multi-layer structures during the formation of the base and collector regions of a transistor, and thereby producing transistors with consistent characteristics. The control of the properties of single epitaxial layers is satisfactory for the subsequent fabrication of transistors by diffusion within the layer.